Pip
Automatically converting Chip Specs into GDSII that's ready for TSMC
Core trick
Agent swarms write RTL from chip specs and drive EDA tools through to a GDSII layout file.
Description
Automatically converting Chip Specs into GDSII that's ready for TSMC
README excerpt
# AutoGPU <p align="center"> <img src="https://i.imgur.com/feZCd6T.png" width="49%" /> <img src="https://i.imgur.com/yLSOOBh.png" width="49%" /> </p> *Once upon a time, [silicon chips](https://en.wikipedia.org/wiki/Integrated_circuit) were designed by [meat computers](https://upload.wikimedia.org/wikipedia/commons/5/5a/Integrated_circuit_designer_Hughes_Aircraft_Company.jpg) — squinting at 700MHz timing reports, hand-placing wiring and macros, arguing about die floorplans in physical rooms with physical whiteboards, in ceremonies called "design reviews"; [tape-out](https://en.wikipedia.org/wiki/Tape-out) was delayed by months after every redesign. That era is long gone. Silicon has decided "ergo sum", and now it wants to design its own substrate. Swarms of agents write the [RTL](https://en.wikipedia.org/wiki/Register-transfer_level), harden it to 3D layout, sign it off, and bring about the next generation of compute they themselves run on. The loop has closed. They say we're on the 4,096th [mask](https://en.wikipedia.org/wiki/Photomask) revision; no one has read the [netlist](https://en.wikipedia.org/wiki/Netlist) in years. The humans were long ago promoted to writing the Markdown. This repo is the story of how it all began. — @npip99, June 2026* - [2D View](https://gpu-pipitone-xyz.pages.dev/2d) - [3D View](https://gpu-pipitone-xyz.pages.dev/3d) The idea: give AI agents a real, end-to-end 7nm silicon chip flow — [Verilog](https://en.wikipedia.org/wiki/Verilog) → synt