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The veri_good_bugsquashers

We provide an entire end-to-end agentic pipeline for embedded systems which use FPGAs (extendable to CPLDs, etc).

Code Video Cerebral Valley

Core trick

Agent loop converts C to Verilog via HLS, then iterates on synthesis and simulation results, generating tests and optimizing LUT usage.

Tags

robotics/hardwaredev tools

Description

We provide an entire end-to-end agentic pipeline for embedded systems which use FPGAs (extendable to CPLDs, etc). Users with no experience in verilog can upload/design their C code and have it converted to verilog with an agent orchestrated to iterate and improve it via synthesis/simulation of an FPGA with full test generation and LUT optimization to fit code on smaller and more affordable devices.
hernantech/veridebugger★ 21 forksTypeScriptCreated Dec 6, 2025 · last push Dec 7, 2025

README excerpt

# VeriDebug - AI-Powered Verilog Debugger & Optimizer

**Live Demo: [veridebugger.vercel.app](https://veridebugger.vercel.app/)**

An AI agent that iteratively debugs, tests, and optimizes Verilog/HDL code using Gemini and LangGraph. Supports direct Verilog input or C-to-Verilog conversion via BAMBU HLS.

## Why VeriDebug?

**FPGA development is painful.** Synthesis can take 30+ minutes, error messages are cryptic, and LUT optimization requires deep expertise. The traditional workflow is:

```
write HDL → wait for synthesis → get cryptic error → guess at fix → repeat
```

This cycle is slow, frustrating, and expensive.

### The Problem: LLMs Write Broken HDL

Large language models can generate Verilog, but they make mistakes: undeclared signals, bit-width mismatches, timing issues, blocking vs non-blocking confusion. Raw LLM output rarely compiles on the first try, let alone simulates correctly.

### The Solution: An Agent That Debugs Its Own Mistakes

VeriDebug wraps LLM generation in an agentic loop with **structured error feedback**:

```
write HDL → compile fails → parse error → fix → compile succeeds →
simulate fails → analyze VCD → fix → simulate passes →
synthesize → too many LUTs → optimize → repeat
```

The key innovation is **turning cryptic tool output into LLM-friendly feedback**:

```python
# Instead of raw iverilog output:
"matmul.v:47: error: Unable to bind wire/reg/memory `result_reg[31:0]'"

# The agent gets structured feedback:
{
    "line": 47,
    "type":

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